This invention relates to the field of computer systems. In particular, this invention is drawn to methods and apparatus for initializing a computer system having maskable address lines.
A computer system typically includes a processor such as a microprocessor that responds to an initialization event by initializing itself to a pre-determined state. The pre-determined state may vary depending upon the type of initialization event. The processor then typically begins executing initialization code located at a pre-determined location or address in memory. The process of initializing a computer system is often referred to as xe2x80x9cbootingxe2x80x9d the computer system.
Some computer system architectures incorporate an address line masking function. In one embodiment, the address line masking function is used to ensure execution compatibility for program code designed for earlier generations of microprocessors having a smaller address space. Various embodiments achieve the address line masking function using address line masking circuitry internal or external to the microprocessor integrated circuit package.
Although the address line masking function is provided to ensure compatibility with program code designed to execute on earlier generation microprocessors, improper application of the address line masking function can result in the microprocessor attempting to boot from a alternate location identified by the masked address lines. Depending upon the contents of the alternate location, the computer system may be rendered inoperable, at least until a subsequent reboot from the correct memory address. Alternatively, enabling the computer system to boot from the alternate address can result in unauthorized initialization code being executed, thus posing a security risk such as enabling an unauthorized application to gain control of the boot process.
In view of limitations of known systems and methods, methods and apparatus for enabling a secure boot process of a computer system having maskable address lines is provided. In particular, one method includes the step of disabling masking of the maskable address line in response to a processor initialization event. In various embodiments the initialization event includes application of power to the processor, a processor RESET, or a processor INIT.
In one embodiment, an apparatus includes a processor coupled to a memory by at least one maskable address line wherein the memory is storing a first initialization instruction. The apparatus includes a mask control wherein the mask control disables masking of the maskable address line before the processor attempts to access the first initialization instruction in response to an initialization event.
In one embodiment, a processor chipset gates a first address mask control with an inhibit bit to provide a second address mask control. The second address mask control is independent of the first address mask control when the inhibit bit is set to a first value. The processor chipset sets the inhibit bit to the first value in response to a processor initialization event.
Other features and advantages of the present invention will be apparent from the accompanying drawings and from the detailed description that follows below.